`include "defines.v"
module ex(
	input wire rst,
	input wire[31:0] reg1_i,
	input wire[31:0] reg2_i,
	input wire[4:0] reg3_addr_i,
	input wire reg3_write_i,
	input wire[`AluOpWidth-1:0] alu_op_i,
	// input wire[`AluSelWidth-1:0] alu_sel_i,
	output reg[31:0] write_data_o,
	output reg write_ce_o,
	output reg[4:0] write_addr_o,
	
	//传给id模块的将要写的数据
	output wire[4:0] ex_id_write_addr_o,
	output wire ex_id_write_ce_o,
	output wire[31:0] ex_id_write_data_o
	
);
	always@(*)
		if(rst == `RstEnable)
		begin
			write_data_o = `ZeroWord;
			write_ce_o = `WriteDisable;
			write_addr_o = 5'b00000;
		end
		else
		begin
			write_ce_o = reg3_write_i;
			write_addr_o = reg3_addr_i;
			case (alu_op_i)
				`ALU_OR_OP:
				begin
					write_data_o = reg1_i | reg2_i;
				end
				`ALU_AND_OP:
				begin
					write_data_o = reg1_i & reg2_i;
				end
				`ALU_XOR_OP:
				begin
					write_data_o = reg1_i ^ reg2_i;
				end
				`ALU_NOR_OP:
				begin
					write_data_o = ~(reg1_i | reg2_i);
				end
				`ALU_LUI_OP:
				begin
					write_data_o = reg1_i;
				end
				`ALU_SLL_OP:
				begin
					write_data_o = reg2_i << reg1_i[4:0];
				end
				`ALU_SRL_OP:
				begin
					write_data_o = reg2_i >> reg1_i[4:0];
				end
				`ALU_SRA_OP:
				begin
					write_data_o = ({32{reg2_i[31]}} << (32 - reg1_i[4:0])) | (reg2_i >> reg1_i[4:0]);
				end
				default:
				begin 
					write_data_o = `ZeroWord;
				end
			endcase
			
		end
		
		
	assign ex_id_write_addr_o = write_addr_o; 
	assign ex_id_write_ce_o = write_ce_o;
	assign ex_id_write_data_o = write_data_o;
endmodule
